Samsung's LPDDR5X-PIM Crams a Processor Into Every DRAM Bank

Samsung used its Hot Chips 2026 talk to unveil LPDDR5X-PIM, a version of its mobile-class DRAM with a small processor wired into each memory bank. In an on-stage demo running Meta's Llama 3.1, that pushed token generation from 27 tokens per second to 81.3, a 3.01x jump, without changing the chip's physical footprint at all.

• LPDDR5X-PIM hits 614 GB/s at the x64, 9600 Mbps operating point, compared to 76.8 GB/s for standard LPDDR5X at the same speed. That's an 8x gap, and it comes from each of the 16 banks computing on its own data instead of funneling everything through one shared external bus.
• On Llama 3.1, task completion time fell from 12.3 seconds to 5.4 seconds, tracking the 3.01x throughput gain from 27 to 81.3 tokens per second.
• It ships in the same 561-ball package as ordinary LPDDR5X, so it slots into existing board designs. No motherboard respin, no new socket. Samsung is pitching it for servers, laptops, and phones.
• It's one of two memory projects Samsung showed at Hot Chips 2026, alongside an updated HBM base die, a sign the company is hedging across more than one approach to the AI memory-bandwidth problem at once.

What did Samsung actually put inside the DRAM?

Every LPDDR5X-PIM chip has 16 banks, and each one now carries its own small compute block: a set of MAC trees (the multiply-accumulate units that do the bulk of the arithmetic in neural network inference) paired with an ALU that handles both floating-point and integer datatypes. Normally, a bank's only job is to store bits and hand them off when asked. Here, each bank can also run part of the math on the data it's already holding, before that data ever has to travel anywhere.

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That's the core idea behind processing-in-memory, PIM for short: instead of hauling every byte across a bus to reach a separate compute die, you let a sliver of compute live right where the data already sits. It's not a new concept in research circles, but putting it into a DRAM standard that's pin-compatible with what's already shipping is the part that makes this presentation notable.

How does that turn into 8x the bandwidth?

Conventional LPDDR5X moves data through one external interface shared by every bank on the chip. Sixteen banks all queue up behind that single door. LPDDR5X-PIM mostly skips the door. When a bank can compute locally, the data it's working on doesn't need to cross the shared bus at all, so the bottleneck that normally throttles the whole chip barely gets touched for that portion of the workload.

That's why Samsung's numbers show 614 GB/s against 76.8 GB/s at the identical x64, 9600 Mbps setting. It's the same physical pins and the same clock, just far less traffic forced through the narrow part of the pipe.

Is this just another name for HBM?

No, and the two solve the bandwidth problem in different ways. HBM stacks multiple DRAM dies on a wide interposer next to the compute die, so you get a much wider physical connection, but the memory itself still just stores and ships bits. LPDDR5X-PIM keeps the standard, narrower LPDDR5X interface and instead gives the memory some ability to compute on its own. Samsung actually showed an evolved HBM base die in a separate Hot Chips 2026 session, which tells you the company isn't betting on one fix. It's working the interposer angle and the in-memory-compute angle at the same time.

Worth being precise about a third approach floating around the same conference: Intel's Crescent Island GPU design, which leans on 160GB of plain LPDDR5X capacity. That's a capacity play, more memory to hold bigger models, not a compute-in-memory play. Different problem, different fix. Don't conflate the two just because both involve LPDDR5X.

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Who does this actually help?

The pitch here is broader than a single datacenter SKU. Because LPDDR5X-PIM keeps the same package as regular LPDDR5X, Samsung is positioning it across servers, laptops, and phones, anywhere token generation is currently choked by how fast data can move between memory and compute rather than by raw compute power. That's the real constraint behind most AI inference slowdowns: the processor often sits idle waiting on memory, not the other way around. A memory chip that removes part of that wait, without forcing a new motherboard or socket, is attractive precisely because it doesn't ask hardware makers to redesign anything around it.

What does this mean for the memory market?

Samsung, SK Hynix, and Micron are all racing to be the bandwidth supplier for AI inference, and they're not converging on one method. HBM remains the default for the biggest accelerators, and Samsung's parallel HBM base die work at this same event shows it isn't stepping away from that fight. PIM is a different bet: cheaper, more familiar packaging that could reach a wider set of products than HBM ever will, since HBM's cost and interposer requirements keep it mostly confined to high-end accelerators. If LPDDR5X-PIM performs in shipping products the way it did on stage, it gives Samsung a card SK Hynix and Micron don't currently have on the table in quite the same form, a bandwidth boost that doesn't require a customer to redesign their board. Whether either competitor has an equivalent PIM project in the wings wasn't part of this disclosure, and it's worth watching for at future events rather than assuming either way.

Our take

The appealing part of this announcement isn't the raw multiplier, it's the packaging. Plenty of PIM research over the years has produced bigger theoretical gains than 3x and gone nowhere, because it demanded new sockets, new controllers, or new software stacks that nobody wanted to commit to. Shipping in the existing 561-ball LPDDR5X footprint removes the single biggest reason those projects stall. That doesn't guarantee LPDDR5X-PIM reaches real products on schedule, memory standards move slowly and JEDEC adoption is its own long process, but it's a more credible path than most PIM proposals get. We'd treat the 3.01x figure as a lab result worth tracking, not a preview of what every AI workload will see once this ships.

Original analysis by GenZTech, drawing on Hot Chips 2026 coverage.