AMD has finally attached names and years to the two CPU generations that follow Zen 6. At its Advancing AI 2026 event on July 23, the company confirmed a Zen 7 EPYC family arriving in 2028 under the codenames Florence, Ferrara and Fidenza, plus a Zen 8 part called Ravenna slated for 2030. Architecture-level slides drew a fresh round of coverage this morning, days after Zen 6 "Venice" itself went on sale. The codenames make the easy headline. The line worth rereading is the one bolted to Florence: it is the first AMD server chip publicly tied to ACE, the AI instruction set AMD and Intel specified jointly, which puts a date on x86 matrix math becoming a shared standard instead of one vendor's extension.

  • Zen 7 lands in 2028 as three EPYC variants: Florence for core count and raw performance, Ferrara for AI host nodes, Fidenza tuned around performance per watt.
  • Zen 8 "Ravenna" is pencilled in for 2030 with an architecture name and nothing else. No node, no core count, no socket, no memory spec.
  • Florence carries ACE, the AI Compute Extensions written by the Intel-and-AMD-led x86 Ecosystem Advisory Group, along with next-generation MRDIMM and LPDDR memory support.
  • The accelerator lane keeps annual cadence: Instinct MI500 in 2027 with EPYC "Verano" and the Helios 500 rack, then MI600 on CDNA Next in 2028.
AMD data center silicon roadmap from 2026 to 2030 Two lanes. EPYC CPUs run Venice in 2026, Verano in 2027, Florence on Zen 7 in 2028 and Ravenna on Zen 8 in 2030. Instinct accelerators run MI455X in 2026, MI500 in 2027 and MI600 in 2028, with nothing disclosed for 2030. ADVANCING AI 2026 · DISCLOSED ROADMAP AMD data center silicon, 2026 to 2030 2026 2027 2028 2030 EPYC CPU INSTINCT Venice Zen 6 · now Verano Helios 500 Florence Zen 7 · ACE Ravenna Zen 8 MI455X shipping MI500 rack refresh MI600 CDNA Next not disclosed Ferrara and Fidenza join Florence on Zen 7 in 2028, aimed at AI host nodes and performance per watt. For Ravenna, AMD named a year and an architecture. Node, cores, socket and memory stayed blank. genztech.blog
Fig 1 AMD's disclosed server silicon cadence. The two orange boxes are what was new this week: Zen 7 in 2028 and Zen 8 in 2030.

What did AMD confirm for 2028 and 2030?

The disclosure came inside AMD's Advancing AI 2026 announcement, the same release where Lisa Su framed the company's pitch around "frontier models, agents and physical AI." Underneath the messaging sits an unusually long roadmap for a CPU vendor, running two full generations past the product that only just shipped.

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Zen 7 is a 2028 story and it arrives as a family rather than a single part. Florence spans both the SP7 and SP8 platforms, mixing Zen 7 and Zen 7c cores, with the SP7 version chasing core count and peak performance while SP8 targets enterprise buyers who care more about performance per system dollar. Ferrara is positioned as the host CPU sitting next to Instinct accelerators, which is why it shows up attached to the Helios 600 rack alongside MI600 GPUs and Pensando networking. Fidenza rounds out the set on efficiency.

Ravenna gets far less. AMD confirmed the name, the Zen 8 architecture and a 2030 window, then stopped. No process node, no socket, no core counts, no memory standard. That is normal for a part four years out, but it is worth naming plainly: the 2030 entry is a commitment to a cadence, not a described product.

The GPU side stayed in lockstep. MI455X is the current generation, powering the Helios rack that AMD describes as 72 Instinct GPUs beside 18 EPYC "Venice" CPUs. MI500 follows in 2027 with Verano, and MI600 on CDNA Next in 2028. Read the two lanes together and the shape is obvious: AMD is selling a rack refresh every year, with the CPU generation turning over roughly every two.

Why is ACE the bigger deal than the codenames?

ACE, short for AI Compute Extensions, came out of the x86 Ecosystem Advisory Group that Intel and AMD lead together. It is a successor to Intel's Advanced Matrix Extensions, and critically it is not backward compatible with AMX. The group chose to specify something new rather than bless the incumbent's existing extension.

That detail carries more weight than it first appears. AMX shipped in Intel Xeon and nowhere else, so software that wanted CPU-side matrix acceleration had to be written against one vendor's silicon or skip the feature entirely. Most frameworks skipped it. A jointly authored spec with both x86 vendors committed to implementing it changes the calculus for anyone maintaining an inference path: the target stops being "Intel servers" and becomes "x86 servers." Intel has already begun posting GCC compiler patches for ACE, which is usually the signal that hardware is a couple of years out rather than a decade.

For Florence specifically, ACE lands next to next-generation MRDIMM and LPDDR memory support. CPU inference is almost always memory bound before it is compute bound, so pairing a denser matrix engine with a bigger memory pipe is the combination that actually moves throughput. Whether AMD or Intel ships ACE silicon first is still open. Neither has announced a shipping part.

Who is each Zen 7 chip actually for?

FlorenceFerraraFidenza
Primary focusCore count and peak performanceAI host node beside InstinctPerformance per watt
PlatformSP7 and SP8Helios 600 rack with MI600Not disclosed
CoresZen 7 and Zen 7cZen 7 familyZen 7 family
Window202820282028

The SP7 and SP8 split is the part enterprise buyers should register. AMD is no longer designing one flagship socket and cutting it down. SP7 chases the density ceiling, the same socket Venice uses today with 16-channel memory and PCIe 6. SP8 exists so a mid-tier server does not have to pay for a platform sized around 256 cores. Anyone whose refresh cycle lands in 2028 now has a reason to ask vendors which socket a quoted box actually uses, because the two tiers will not be interchangeable.

What does a roadmap to 2030 signal for the market?

AMD (NASDAQ: AMD) is not really selling chips on this slide, it is selling predictability. Hyperscalers plan data center power and floor space years ahead, and a vendor that can name its 2028 and 2030 parts is easier to build a five-year plan around. That is the same argument Nvidia (NASDAQ: NVDA) has been making with its annual accelerator cadence, and AMD is now matching the format lane for lane with Helios 500 and Helios 600.

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The read for Intel (NASDAQ: INTC) is more awkward. Its own matrix extension is being superseded by a spec it co-authored, and the joint standard removes one of the few remaining reasons a CPU inference workload had to run on Xeon. The signal for investors is execution rather than architecture: Venice shipped on the July window AMD promised, so the 2027 and 2028 dates carry more credibility today than the same slide would have carried two years ago. Watch whether Verano holds its 2027 slot, because that is the first date on this roadmap that can actually slip.

What to watch · 2027 to 2028
  • The unnamed node. AMD said "next-generation process" for Florence and refused to name it. Venice is on TSMC 2nm, so the interesting question is whether Florence jumps to A16 class or stays on a 2nm derivative.
  • First ACE silicon. Intel is already upstreaming ACE compiler support. Whoever ships the first ACE-capable core sets the de facto reference implementation.
  • Ravenna's blank fields. A 2030 entry with no node, socket or core count is a placeholder. It becomes a plan the day AMD attaches a socket to it.
  • Client Zen 7. Nothing was said about Ryzen. Zen 6 desktop already slipped toward CES 2027, so consumer Zen 7 timing is entirely unmapped.

Where this could still slip

Roadmaps this long are marketing documents as much as engineering ones, and AMD has quietly moved dates before. The consumer side of Zen 6 is the recent example: server parts hit their window while Ryzen drifted to roughly CES 2027. Nothing on this slide is a shipping commitment, and the further right you read, the less it constrains.

Still, there is a difference between a codename with a year and a codename with a year plus an instruction set, a memory standard and a named rack platform. Florence has all four. Ravenna has one. Treat 2028 as a plan and 2030 as an intention, and this roadmap is a reasonable thing to build against. The single most useful takeaway is not that Zen 7 exists, it is that CPU-side AI acceleration on x86 now has a shared target and a date, which is more than the last decade of AMX managed.

For context on the generation that just shipped, see our coverage of Zen 6 EPYC "Venice" and its 256-core ceiling.

Primary sources

Original analysis by GenZTech. Reporting: Tom's Hardware, AMD CPU architecture roadmap through 2028.